{"id":2592,"date":"2021-04-19T12:17:47","date_gmt":"2021-04-19T16:17:47","guid":{"rendered":"https:\/\/asplos-conference.org\/?page_id=2592"},"modified":"2021-04-20T19:57:38","modified_gmt":"2021-04-20T23:57:38","slug":"awards","status":"publish","type":"page","link":"https:\/\/asplos-conference.org\/awards\/","title":{"rendered":"\ud83c\udfc6 Awards"},"content":{"rendered":"\n<h1><strong>\ud83c\udf96\ufe0f<strong>Influential Paper<\/strong>s<\/strong><\/h1>\n\n\n\n<ul style=\"padding-left: 30px;list-style-type: none;\">\n<li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/abs\/10.1145\/36206.36201\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002A VLIW Architecture for a Trace Scheduling Compiler <br>\u2003\u2002ASPLOS 1987 &#8212; <i>Robert P. Colwell, Robert P. Nix, John J. O&#8217;Donnell, David B. Papworth, Paul K. Rodman<\/i>.<\/li>\n<li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/10.1145\/106973.106981\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002The Cache Performance and Optimizations of Blocked Algorithms <br>\u2003\u2002ASPLOS 1991 &#8212; <i>Monica S. Lam, Edward E. Rothberg, Michael E. Wolf<\/i>.<\/li>\n<li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/10.1145\/143371.143490\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation <br>\u2003\u2002ASPLOS 1992 &#8212; <i>Shien-Tai Pan, Kimming So, Joseph T. Rahmeh<\/i>.<\/li>\n<li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/10.1145\/248209.237173\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002Value Locality and Load Value Prediction <br>\u2003\u2002ASPLOS 1996 &#8212; <i>Mikko H. Lipasti, Christopher B. Wilkerson, John Paul Shen<\/i>.<\/li>\n<\/ul>\n\n\n\n<h1><strong>\ud83c\udf96\ufe0fDistinguished Papers<\/strong><\/h1>\n\n\n\n<ul style=\"padding-left: 30px;list-style-type: none;\"><li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3445814.3446695\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002Who&#8217;s Debugging the Debuggers? Exposing Debug Information Bugs in Optimized Binaries<\/li>\n<li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3445814.3446729\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002Computing with Time: Microarchitectural Weird Machines<\/li>\n<li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3445814.3446732\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002Autonomous NIC Offloads<\/li>\n<li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3445814.3446748\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002VSync: Push-Button Verification and Optimization for Synchronization Primitives on Weak Memory Models<\/li>\n<li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3445814.3446753\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002Neural Architecture Search as Program Transformation Exploration<\/li>\n<li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3445814.3446755\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002Compiler-Driven FPGA Virtualization with SYNERGY<\/li><\/ul>\n\n\n\n<h1><strong>\ud83c\udf96\ufe0fDistinguished Artifacts<\/strong><\/h1>\n\n\n\n<ul style=\"padding-left: 30px;list-style-type: none;\"><li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3445814.3446714\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002Benchmarking, analysis, and optimization of serverless function snapshots<\/li>\n<li><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3445814.3446744\&quot;" target=\"blank\" rel=\"noopener\">\ud83d\udd17<\/a>\u2002Fast, Flexible and Comprehensive Bug Detection for Persistent Memory Programs<\/li><\/ul>\n","protected":false},"excerpt":{"rendered":"<p>\ud83c\udf96\ufe0fInfluential Papers \ud83d\udd17\u2002A VLIW Architecture for a Trace Scheduling Compiler \u2003\u2002ASPLOS 1987 &#8212; Robert P. Colwell, Robert P. Nix, John J. O&#8217;Donnell, David B. Papworth, Paul K. Rodman. \ud83d\udd17\u2002The Cache &hellip; <\/p>\n<p class=\"link-more\"><a href="https://asplos-conference.org/2021/wp-json/wp/v2/pages/\&quot;https:\/\/asplos-conference.org\/awards\/\&quot;" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;\ud83c\udfc6 Awards&#8221;<\/span><\/a><\/p>\n","protected":false},"author":12,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"_links":{"self":[{"href":"https:\/\/asplos-conference.org\/wp-json\/wp\/v2\/pages\/2592"}],"collection":[{"href":"https:\/\/asplos-conference.org\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/asplos-conference.org\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/asplos-conference.org\/wp-json\/wp\/v2\/users\/12"}],"replies":[{"embeddable":true,"href":"https:\/\/asplos-conference.org\/wp-json\/wp\/v2\/comments?post=2592"}],"version-history":[{"count":8,"href":"https:\/\/asplos-conference.org\/wp-json\/wp\/v2\/pages\/2592\/revisions"}],"predecessor-version":[{"id":2609,"href":"https:\/\/asplos-conference.org\/wp-json\/wp\/v2\/pages\/2592\/revisions\/2609"}],"wp:attachment":[{"href":"https:\/\/asplos-conference.org\/wp-json\/wp\/v2\/media?parent=2592"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}